day, December 22 2011 Intel Xeon E5-2690 Sandy Bridge-EP Performance Leaked

We sourced a presentation, allegedly by Intel, detailing its Sandy Bridge-EP platform, and giving out early performance figures. After successful and trouble-free launches of its Sandy Bridge architecture across all PC form-factors, including the recently-launched Core i7 "Sandy Bridge-E" HEDT (high-end desktop), Intel is taking the architecture to its ultimate market, enterprise, where processors derived from it will make up new lines of Intel Xeon processor families. Intel has two branches of enterprise variations the architecture, Sandy Bridge-EN, designed for high-density, low-power servers, and Sandy Bridge-EP, designed for high-performance servers and workstations. Sandy Bridge-EP is multi-socket capable.

Sandy Bridge-EP uses essentially the same piece of silicon as Sandy Bridge-E, but enabled with several of its features otherwise off limits to the Core processor family. These include twoQuickPath Interconnect (QPI) links, which facilitate high-bandwidth inter-socket communication in multi-socket systems, up to eight cores, sixteen threads enabled by HyperThreading, and up to 20 MB of L3 cache memory. Like its Core family cousins, Xeon Sandy Bridge-EP packs a quad-channel DDR3 integrated memory controller, and PC3-12800 (DDR3-1600 MHz) is its optimal memory standard, but unlike it, supporting up to 768 GB of memory (by two sockets, eight DDR3 channels in all, LRDIMMs). Other key features are listed in the first slide below.

 

 Performance figures follow.

In its presentation, Intel claims up to 80 percent performance increments over the previous-generation Westmere-EP platform. A single Xeon X5690 six-core processor was set as a base line, and compared to a single Xeon E5-2690 eight-core processor. The chips were put through several enterprise performance and throughput tests, including OLTP Database (TPC-C Oracle), Middle-Tier Java (SPECjbb 2005), Integer Throughput (SPECint_base2006), Floating Point Throughput (SPECfp_rate_base2006), Memory Bandwidth (STREAM_MP Triad), and Matrix Multiplication (Linpack). Its results are graphed below.

Performance figures follow.

In its presentation, Intel claims up to 80 percent performance increments over the previous-generation Westmere-EP platform. A single Xeon X5690 six-core processor was set as a base line, and compared to a single Xeon E5-2690 eight-core processor. The chips were put through several enterprise performance and throughput tests, including OLTP Database (TPC-C Oracle), Middle-Tier Java (SPECjbb 2005), Integer Throughput (SPECint_base2006), Floating Point Throughput (SPECfp_rate_base2006), Memory Bandwidth (STREAM_MP Triad), and Matrix Multiplication (Linpack). Its results are graphed below.