The idea behind 3DS is to use specially designed and manufactured master-and-slave DRAM die, with only the master die interfacing with the external memory controller. 3DS technology uses optimized DRAM die, single DLL per stack, reduced active logic, single shared external I/O, improved timing, and reduced load to the external world. This combination of features can improve timing, bus speeds, and signal integrity while lowering both power consumption and system overhead for next-generation modules, according to Micron.The video below demonstrates a timing limitation when reading from one memory rank and then another, which causes a one-cycle gap on the data bus. It may not sound much, but repeated billions of times, it all adds up:
The 3DS technology resolves this problem by allowing the 3DS device to accept Read commands to different ranks, which keeps the data bus full by eliminating these single-cycle gaps, as Aftab Farooqi of Micron Technology explains:
In the second case, we are observing how data is continuous when the system issues consecutive Read commands on the same rank. A 3DS-optimized system will similarly take advantage of this tighter timing and be able to see improved data bus utilization and bandwidth when reading from different banks.Note that this technology is different to the 3D Hybrid Memory Cube technology announced jointly by IBM and Micron and it looks like HMC will actually compete with 3DS.
3D chip technology seems to be all the rage at the moment, what with Intel's Tri-Gate tech in the upcoming Ivy Bridge CPU's and now this, it sounds like a very interesting development and TechPowerUp will be sure to report updates as they come in.