After technical analysis, the PCI-SIG has determined that 16 GT/s on copper, which will double the bandwidth over the PCIe 3.0 specification, is technically feasible at approximately PCIe 3.0 power levels. The data also confirms that a 16GT/s interconnect can be manufactured in mainstream silicon process technology and can be deployed with existing low-cost materials and infrastructure, while maintaining compatibility with previous generations of PCIe architecture. In addition, the PCI-SIG will investigate advancements in active and idle power optimizations, key issues facing the industry.
"The PCI Express architecture has become the de facto I/O technology within the industry, in large part due to PCI-SIG's dedication to I/O innovation and the insight of those who defined earlier versions in such an extensible manner," said Nathan Brookwood, research fellow at Insight 64. "Like its predecessors, the PCIe 4.0 architecture is well positioned to preserve the industry's investments in earlier generations of PCI Express specifications while extending the technology in a manner that enables new applications and usage models."
Approximately 24 billion lanes of PCIe have shipped in the marketplace since its introduction−a strong testament to the industry's reliance on PCIe architecture as an open bus standard now and for the future. This next-generation PCIe architecture, while doubling the data rate, will maintain its position as a low-cost, high-performance I/O technology. PCIe 4.0 technology will maintain backward compatibility with previous PCIe architectures and provide the optimum design point for high-volume platform I/O implementations across a wide range of existing and emerging applications. The PCIe 4.0 specification will address the many applications pushing for increased bandwidth at a low cost including server, workstation, desktop PC, notebook PC, tablets, embedded systems, peripheral devices, high-performance computing markets and more.
"Experts in the PCIe Electrical Workgroup carefully analyzed a number of target bit rates for the next generation of PCIe architecture, taking into consideration several key factors, including our ability to continue using low-cost materials. We have concluded that 16 GT/s is a feasible technical solution that satisfies our member companies' requirements," said Al Yanes, PCI-SIG chairman. "While the preliminary analysis is encouraging, a lot more challenging work lies ahead in developing the specifications. The PCI-SIG looks forward to providing our members with a specification that not only satisfies their high performance
The final PCIe 4.0 specifications, including form factor specification updates, are expected to be available sometime in the 2014-2015 timeframe.